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SLNO
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IEEE – VLSI DESIGN &
IMPLEMENTATION
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DOMAIN
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MDV01
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Design of Neural Networks With Hyperbolic Tangent Activation Function
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Neural Networks
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MDV02
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High performance Low-Power Pulse-Triggered Flip-Flop Design Based on a
Signal Feed-Through Scheme
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Low power design
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MDV03
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Analysis and calculation of Ultra-High Throughput Low-Power Packet
Classification
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MDV04
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Design, Test and evaluation of Framed Trace-Buffer system for FPGA Testing
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MDV05
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Reliable and time based Light-Weight On-Chip Structure for Measuring
Timing Uncertainty Induced by Noise in Integrated Circuits
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Testing & Debugging
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MDV06
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Design of Low cost and AI based approach of On-Chip Oscilloscope to
Measure Jitter, Glitch and Skew of high speed signals
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MDV07
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Design of Gated-Latch Utilization Technique for Clock-Tree Power Optimization
system
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MDV08
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On the Automatic Generation of Optimized Software-Based Self-Test
Programs for VLIW Processors
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MDV09
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Measure of Variation-Aware Variable Latency Design for all applications
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MDV10
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Indepth performance measure of On Deadlock Problem of On-Chip Buses
Supporting Out-of-Order Transactions
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System On Chip
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MDV11
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Implementation of Delay Test for Diagnosis of Power Switches
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MDV12
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Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating
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MDV13
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Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal
Matrix Code
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Design Analyzing
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MDV14
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Reconfigurable High-Resolution All-Digital Duty-Cycle Corrector with
auto correct module
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Oscillators & Circuits
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MDV15
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Software/Hardware Parallel Long-Period Random Number Generation
Framework Based on the WELL Method
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MDV16
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Design of Cell-Based Process Resilient Multiphase Clock Generation
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MDV17
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LASIC: Loop-Aware Sleepy Instruction Caches Based on STT-RAM Technology
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Memory Mapping
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MDV18
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FPGA based Process-Resilient Low-Jitter All-Digital PLL via Smooth
Code-Jumping
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Clock synthesizers
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MDV19
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Low-Complexity Reconfigurable Fast Filter Bank for Multi-Standard
Wireless Receivers
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Signal Processing
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MDV20
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Use of SSTA Tools for Evaluating BTI Impact on Combinational Circuits
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Tool Design
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