Thursday, 13 November 2014

LATEST VLSI TOPICS





SLNO
IEEE – VLSI DESIGN & IMPLEMENTATION
DOMAIN

MDV01
Design of Neural Networks With Hyperbolic Tangent Activation Function
Neural Networks


MDV02
High performance Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal Feed-Through Scheme
Low power design

MDV03
Analysis and calculation of Ultra-High Throughput Low-Power Packet Classification

MDV04
Design, Test and evaluation of Framed  Trace-Buffer system  for FPGA Testing

MDV05
Reliable and time based Light-Weight On-Chip Structure for Measuring Timing Uncertainty Induced by Noise in Integrated Circuits
Testing & Debugging

MDV06
Design of Low cost and AI based approach of On-Chip Oscilloscope to Measure Jitter, Glitch and Skew of high speed signals

MDV07
Design of Gated-Latch Utilization  Technique for Clock-Tree Power Optimization system

MDV08
On the Automatic Generation of Optimized Software-Based Self-Test Programs for VLIW Processors

MDV09
Measure of Variation-Aware Variable Latency Design for all applications




MDV10
Indepth performance measure of On Deadlock Problem of On-Chip Buses Supporting Out-of-Order Transactions
System On Chip
MDV11
Implementation of Delay Test for Diagnosis of Power Switches
MDV12
Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating
MDV13
Enhanced Memory Reliability Against Multiple Cell Upsets Using Decimal Matrix Code
Design Analyzing
MDV14
Reconfigurable High-Resolution All-Digital Duty-Cycle Corrector with auto correct module
Oscillators & Circuits
MDV15
Software/Hardware Parallel Long-Period Random Number Generation Framework Based on the WELL Method
MDV16
Design of Cell-Based Process Resilient Multiphase Clock Generation
MDV17
LASIC: Loop-Aware Sleepy Instruction Caches Based on STT-RAM Technology
Memory Mapping
MDV18
FPGA based Process-Resilient Low-Jitter All-Digital PLL via Smooth Code-Jumping
Clock synthesizers
MDV19
Low-Complexity Reconfigurable Fast Filter Bank for Multi-Standard Wireless Receivers
Signal Processing
MDV20
Use of SSTA Tools for Evaluating BTI Impact on Combinational Circuits
Tool Design



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