BIST DESIGN

BIST DESIGN

Built in Self Test -  Implementations

A memory BIST unit consists of a controller to control the flow of the test sequences and also other components to generate the necessary test data.

The memory BIST logic can be classified into three parts, hard wired based, microcode based and processor based. (Cheng. A, 2002).

·         Hardwired based BIST

The hard wired based BIST can be well explained in the block diagram below. It is basically the hardware realisation of a selected memory test algorithm; it is usually in the form of a finite state machine (FSM).

The disadvantage can be that for a minor change in the test pattern whole of the system needs to be modified. (Cheng. A, 2002).

Fig.2 Hardwired based BIST (Cheng. A, 2002).

·  Micro Code based BIST

A micro code based BIST is a set of predefined set of instructions which is used as a set of test algorithms. This allows selected change in the test algorithm without disturbing the hardware of the controller; the major disadvantage can be the higher logic overhead for the controller. (Cheng. A, 2002).

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    Processor based BIST

In the SOC memory most of the universal cores contain memory such as RAM, DRAM etc. As we have seen the hardwired based BIST reduces the circuit overhead but it is not possible to have a separate BIST for all the memories, therefore a new type of BIST that uses the on chip microprocessor was proposed.

The processor based BIST is developed by executing a assembly language program into the on chip microprocessor to generate test patterns. (Cheng. A, 2002).